FABRICATION METHOD OF SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE

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United States of America Patent

SERIAL NO

11861089

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ATTORNEY / AGENT: (SPONSORED)

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Abstract

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To permit electrical testing of a semiconductor integrated circuit device having test pads disposed at narrow pitches probes in a pyramid or trapezoidal pyramid form are formed from metal films formed by stacking a rhodium film and a nickel film successively. Via through-holes are formed in a polyimide film between interconnects and the metal films, and the interconnects are electrically connected to the metal films. A plane pattern of one of the metal films equipped with one probe and through-hole is obtained by turning a plane pattern of the other metal film equipped with the other probe and through-hole through a predetermined angle.

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Patent Owner(s)

Patent OwnerAddress
RENESAS ELECTRONICS CORPORATIONKANAGAWA JAPAN

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
HASEBE, Akio Kodaira, JP 104 1807
HASEGAWA, Yoshiaki Maebashi, JP 87 1041
MAJIMA, Toshiyuki Yokohama, JP 22 88
MATSUMOTO, Hideyuki Higashimurayama, JP 87 564
MOTOYAMA, Yasuhiro Hachioji, JP 26 199
NARIZUKA, Yasunori Hiratsuka, JP 40 480
OKAMOTO, Masayoshi Ryuou, JP 81 892
SHIBATA, Ryuji Higashiyamato, JP 26 404
YABUSHITA, Akira Yokohama, JP 23 166
YORISAKI, Shingo Hachioji, JP 12 205

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