Importance

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Abstract

Programmable routing structures to couple physical memory nodes to logical memory nodes in embedded multi-port memory FPGA's are disclosed. In a first embodiment, a plurality of physical domain nodes couples a plurality of variable node sets in a logical read domain, wherein a configuration element activates one of the sets and selects a fixed input or an address signal to decode the data read. In a second embodiment, a plurality of physical domain nodes couples a plurality of variable node sets in a logical write domain, wherein a configuration element activates one of the sets and couples a fixed input or an address signal to an enable signal of a driver device to decode the data written. A third embodiment provide logical read and logical write functions for a single port in a multi-port physical memory array, wherein the logical read data width and the logical write data width can be independently configured, and wherein the read and write functions share common address lines.

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First Claim