Memory refresh apparatus and method
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United States of America Patent
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Dec 13, 2011
Grant Date -
Jan 31, 2008
app pub date -
Jul 31, 2006
filing date -
Jul 31, 2006
priority date (Note) -
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Abstract
A system and method are provided. The system and method simulate a DRAM memory circuit using an interface circuit connected to a plurality of other DRAM memory circuits. In response to the receipt of a refresh control signal, a first refresh control signal is sent to a first subset of the plurality of other DRAM memory circuits and a second refresh control signal is sent to a second subset of the plurality of other DRAM memory circuits.
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