Method and system for handling process related variations for integrated circuits based upon reflections

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United States of America Patent

PATENT NO 7853904
SERIAL NO

11768891

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Abstract

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Disclosed is an approach for modeling and correcting for the effects of reflections during lithography processing. Thickness differences across the surfaces in different integrated circuit layers may result in reflectance-related variations. The variations may be modeled and accounted for during the design process for the integrated circuit.

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Patent Owner(s)

  • CADENCE DESIGN SYSTEMS, INC.

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
White, David San Jose, US 205 6959

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