Transformation of IC designs for formal verification

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United States of America Patent

PATENT NO 8453083
APP PUB NO 20080028347A1
SERIAL NO

11495136

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ATTORNEY / AGENT: (SPONSORED)

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Abstract

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A memory is encoded with data that represents a reference IC design, a retimed IC design, and logical relationships, wherein at least one logical relationship describes combinational logic without reference to structural information, such as actual cells that have been instantiated in the IC designs. The logical relationships are used to instantiate logic described therein, and to define one or more black boxes as being functionally inverse of the logic. Each instantiated logic and its functionally inverse black box are thereafter added to the reference IC design to obtain a transformed reference IC design. A transformed retimed IC design is also obtained by addition of the instantiated logic(s) and functionally inverse black box(es) to the retimed IC design. These two transformed IC designs are then supplied to an equivalence checker, for formal verification.

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Patent Owner(s)

Patent OwnerAddress
SYNOPSYS INC675 ALMANOR AVENUE SUNNYVALE CA 94085

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Hiraoglu, Muzaffer Chelmsford, US 17 1319
Zepter, Peter Wilhelm Josef Mountain View, US 3 70

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