Importance

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Abstract

Password recovery utilizes a hardware accelerator operating in connection with a host computer system that runs software to generate and format password candidates for computational processing. The hardware accelerator accepts formatted password candidates and can store a number of these candidates in a memory that is managed by a memory controller. A processing matrix is made up of a number of FPGAs which each can be programmed to run a number of computational blocks that are configured to 'consume' or process a request packet containing a single password candidate. This multiple FPGA, multiple computational block configuration allows parallel processing of numerous password candidates by the hardware accelerator, a process that is normally computationally expensive. Processing of a request packet by a computational block generates a response packet that includes computational results corresponding to the single password candidate contained in the consumed request packet. The FPGAs can be arrayed using a nearest neighbor protocol in some embodiments. The request and response packets can be stored in and retrieved from the memory using a memory controller. The response packets retrieved from the memory can be unpacked by software to yield data to be evaluated by password recovery software running on the host computer system.

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First Claim