Dual charge storage node with undercut gate oxide for deep sub-micron memory cell
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United States of America Patent
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Issued Date -
Mar 13, 2008
app pub date -
Feb 5, 2007
filing date -
Feb 4, 2006
priority date (Note) -
Abandoned
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Abstract
An embodiment of the present invention is directed to a memory cell. The memory cell includes a stack formed over a substrate. The stack includes a gate oxide layer and an overlying polycrystalline silicon layer. The stack further includes first and second undercut regions formed under the polycrystalline silicon layer and adjacent to the gate oxide layer. The memory cell further includes a first charge storage element formed in the first undercut region and a second charge storage element formed in the second undercut region.
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