Non-volatile memory with reduced erase/write cycling during trimming of initial programming voltage
Number of patents in Portfolio can not be more than 2000
United States of America Patent
Stats
-
Oct 20, 2009
Grant Date -
Mar 13, 2008
app pub date -
Sep 12, 2006
filing date -
Sep 12, 2006
priority date (Note) -
In Force
status (Latency Note)
Importance
Abstract
High performance non-volatile memory devices have the programming voltages trimmed for individual types of memory pages and word lines. A group of word lines within each erasable block of memory are tested successive program loops to minimize the problem of incurring excessive number of erase/program cycles. An optimum programming voltage for a given type of memory pages is derived from statistical results of a sample of similar of memory pages.
First Claim
Family
International Classification(s)
Cited Art Landscape
Patent Citation Ranking
Advertisement
Advertisement
Advertisement
Recipient Email Address
Recipient Email Address
Comment
Recipient Email Address
Add to Portfolio(s)
To add this patent to one, or more, of your portfolios, simply click the add button.
This Patent is in these Portfolios:
Add to additional portfolios:
Last Refreshed On:
Changes done successfully