Insulated-gate field-effect thin film transistors
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United States of America Patent
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Nov 19, 2007
filing date -
Jul 8, 2002
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Abstract
A semiconductor thin film Gated-FET device, comprising: a resistive thin film channel region positioned between a source and a drain region, said channel region comprising a lower level of said source and drain majority carrier type; and a gate region coupled to the channel region by a dielectric region, wherein a first gate voltage modulates the channel resistance to a substantially non-conductive state by fully depleting majority carriers from the thin film channel region. Said device, wherein a second gate voltage modulates the channel resistance to a substantially conductive state by leaving adequate majority carriers in the thin film layer channel region.
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