Importance

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Abstract

A frame rate controller method and system are provided. Aspects the exemplary embodiment include a data separator responsive to receiving display data comprising frames of digital pixel data for separating the display data into an integer part comprising upper bits of the display data, and a fraction part (Din_f) comprising lower bits of the display data; a high/low generator responsive to receiving the integer part for generating a data out high value and a data out low value, wherein the data out high value equals the integer part plus one and the low value equals the integer part; a multiplier responsive to receiving a frame counter value (Fc) and the Din_f for multiplying and outputing a first multiplication result of Din_f.times.(Fc+1), and a second multiplication result of Din_f.times.Fc; a pixel sequence LUT containing a pattern of sequence numbers, wherein the pixel sequence LUT outputs one of the sequence numbers based on horizontal pixel counter and vertical line counter values; a comparator for generating a code based on a comparison of the sequence number output from the pixel sequence LUT and the first and second values output from the multiplier, wherein the code comprises a first value and a second value; and a multiplexer for receiving the code and the data out high value and the data out low value from the high/low generator, and outputting the data out high value if the code equals the first value, and outputting the data out low value if the code equals the second value.

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First Claim