Flash memory cell structure for increased program speed and erase speed
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United States of America Patent
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Issued Date -
Apr 3, 2008
app pub date -
Sep 28, 2006
filing date -
Sep 28, 2006
priority date (Note) -
Abandoned
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Abstract
According to one exemplary embodiment, a structure, for example a flash memory cell, comprises a transistor gate dielectric stack situated on a semiconductor substrate. The transistor gate dielectric stack includes a bottom oxide layer, a silicon-rich nitride layer situated on the bottom oxide layer, a low silicon-rich nitride layer situated on the silicon-rich nitride layer, and a top oxide layer situated on the low silicon-rich nitride layer. This embodiment results in a nitride based flash memory cell having improved program speed and retention while maintaining a high erase speed. In another embodiment, a flash memory cell may further comprise a high-K dielectric layer situated on the transistor gate dielectric stack.
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