Refresh management of memory modules
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United States of America Patent
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Oct 22, 2013
Grant Date -
May 8, 2008
app pub date -
Oct 30, 2007
filing date -
Jul 31, 2006
priority date (Note) -
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Abstract
One embodiment sets forth an interface circuit configured to manage refresh command sequences that includes a system interface adapted to receive a refresh command from a memory controller, clock frequency detection circuitry configured to determine the timing for issuing staggered refresh commands to two or more memory devices coupled to the interface circuit based on the refresh command received from the memory controller, and at least two refresh command sequence outputs configured to generate the staggered refresh commands for the two or more memory devices.
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