Importance

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Abstract

A system comprises an embedded processor A, a processor or equipment B and a FPGA/CPLD module, wherein a synchronous serial port of the embedded processor A is connected with the FPGA/CPLD module; in which a transmission clock and transmission frame synchronization signal are taken as output, while a receiving clock and receiving frame synchronization signal are taken as input; and a communication interface of the processor or equipment B is connected with the FPGA/CPLD module. This system ensures that the data transmitting party always take initiatives during communications with processor of equipment B. Via the FPGA/CPLD module, the system may interface with other systems through different communication protocols, such that the system need not modify its solutions to adapt to different protocols, but only upgrades the logic of the FPGA/CPLD to adapt to the new interfaces. As such, a high-speed, reliable and flexible communication mechanism is established.

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First Claim