BIT LINE PRE-SETTLEMENT CIRCUIT AND METHOD FOR FLASH MEMORY SENSING SCHEME
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United States of America Patent
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app pub date -
Feb 26, 2008
filing date -
Nov 16, 2005
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Abandoned
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Abstract
A flash memory array includes a reference bit line on which a reference current is imposed. During read operation, bit lines selected for reading are connected to current-to-voltage converters, each of which generates an output voltage based upon the input current flowing in the bit line. The output voltage of the current-to-voltage converter is compared to a reference voltage derived from the output of a reference current-to-voltage converter whose input is driven by a reference current on a reference bit line. Any cell that conducts more current than the reference current will be regarded as an erased cell. Conversely, any cell that conducts less current than the reference current will be regarded as a programmed cell.
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