Retention margin program verification
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United States of America Patent
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Jan 26, 2010
Grant Date -
Jul 3, 2008
app pub date -
Dec 28, 2006
filing date -
Dec 28, 2006
priority date (Note) -
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Abstract
A memory system, comprising an array of storage elements divided into logical blocks and pages within said logical blocks and a managing circuit is provided. The managing circuit is in communication with said array of storage elements and performs programming and reading operations. The programming operations include programming a plurality of multi-state storage data. The reading operations include defining an retention margin between adjacent data thresholds, determining whether bits are present in a portion of the data retention margin, and if the number of bits in the portion of retention margin exceeds a threshold, generating an error.
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