Method for realizing an electric linkage in a semiconductor electronic device between a nanometric circuit architecture and standard electronic components

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United States of America Patent

PATENT NO 7945867
APP PUB NO 20080174024A1
SERIAL NO

11971147

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Abstract

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A method for realizes electric connections in a semiconductor electronic device between a nanometric circuit architecture and standard electronic components. The method includes: providing a nanometric circuit architecture comprising a succession of conductive nanowires substantially parallel to each other and extended along a direction x; realizing, above the succession, an insulating layer; opening, in the insulating layer, a window of nanometric width b extended along a direction inclined by an angle α with respect to the direction x to substantially cross the whole succession of nanowires, with exposure of a succession of exposed portions of the nanowires, one for each nanowire; realizing, above the insulating layer, a plurality of conductive dies extended along a direction y substantially orthogonal to the direction x and addressed towards the standard electronic components, each of such dies overlapping said window onto a respective exposed portion of a nanowire with obtainment of a plurality of contacts realizing said electric connections.

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Patent Owner(s)

  • STMICROELECTRONICS S.R.L.

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Cerofolini, Gianfranco Milan, IT 24 241
Mascolo, Danilo Ercolano, IT 20 197

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