Memory cell provided with dual-gate transistors, with independent asymmetric gates
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United States of America Patent
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Feb 14, 2012
Grant Date -
Jul 24, 2008
app pub date -
Dec 26, 2007
filing date -
Dec 28, 2006
priority date (Note) -
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Abstract
The invention concerns a random access memory cell comprising: at least one first plurality of symmetrical dual-gate transistors (TL1.sub.T, TL1.sub.F, TD1.sub.T, TD1.sub.F, TL2.sub.T, TL2.sub.F) forming a flip-flop, at least a first asymmetric dual-gate access transistor (TA1.sub.T, TAW1.sub.T) and at least a second asymmetric dual-gate access transistor (TA1.sub.F, TAW1.sub.F) disposed respectively between a first bit line (BL.sub.T, WBL.sub.T) and a first storage node (T), and between a second bit line (BL.sub.F, WBL.sub.F) and a second storage node (F), a first gate of the first access transistor (TA1.sub.T, TAW1.sub.T) and a first gate of the second access transistor (TA1.sub.F, TAW1.sub.F) being connected to a first word line (WL, WWL) able to route a biasing signal, a second gate (TA1.sub.F, TAW1.sub.F) of the first access transistor connected to the second storage node (F) and a second gate of the second access transistor connected to the first storage node (T).
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