Synthesized assertions in a self-correcting processor and applications thereof
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United States of America Patent
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Issued Date -
Jul 24, 2008
app pub date -
Jan 19, 2007
filing date -
Jan 19, 2007
priority date (Note) -
Abandoned
status (Latency Note)
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Abstract
The present invention provides one or more synthesized assertions in a self-correcting processor, and applications thereof. In an embodiment, a synthesized assertion detects a mismatch between actual processor behavior and specified or expected processor behavior. When unexpected processor behavior is encountered, the synthesized assertion alters operation of the processor and causes the processor to behave in the specified or expected manner. Synthesized assertions in accordance with the present invention can detect and correct, for example, exception processing errors, instruction address errors, instruction opcode errors, and errors that can cause a processor to stall, as well as various other types of errors.
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