FPGA ARCHITECTURE WITH THRESHOLD VOLTAGE COMPENSATION AND REDUCED LEAKAGE
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United States of America Patent
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Issued Date -
Jul 31, 2008
app pub date -
Aug 30, 2007
filing date -
Aug 31, 2006
priority date (Note) -
Abandoned
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Abstract
A method for providing transistor threshold voltage compensation in an FPGA integrated circuit with a plurality of programmable circuit blocks includes measuring the effective transistor threshold voltage values of each programmable circuit block and adjusting the effective transistor threshold voltage values of each programmable circuit block to compensate for the difference between the measured effective transistor threshold voltage value and the target effective transistor threshold voltage value.
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