US Patent Application No: 2008/0185,708

Number of patents in Portfolio can not be more than 2000

Stackable semiconductor package having metal pin within through hole of package

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Abstract

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The present invention provides a stackable semiconductor having an interconnect board for providing electrical interconnections, the package includes a plurality of solders disposing onto the interconnect board; and a conducting metal pin passing through each solder and the interconnect board, the metal pins having at least one end disposes on the semiconductor package, wherein when a plurality of the stackable semiconductor packages are stacked together, the exposed end of the corresponding conducting pins are bonded together. A method of manufacturing the same is also provided.

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First Claim

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Patent Owner(s)

Patent OwnerAddressTotal Patents
BRIDGE SEMICONDUCTOR CORPORATIONTAIPEI87

International Classification(s)

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Chen, Cheng-Chung Taipei, TW 54 333
Hock, Tan Chin Singapore, SG 1 12
Lin, Charles WC Yunghe, TW 94 365
Wang, Chia-Chung Hsinchu, TW 112 469

Cited Art Landscape

Patent Info (Count) # Cites Year
 
Other [Check patent profile for assignment information] (1)
* 2006/0252,180 Method for a low profile multi-IC chip package connector 1 2006
 
GREATBATCH LTD. (1)
* 2006/0259,093 HERMETIC FEEDTHROUGH TERMINAL ASSEMBLY WITH WIRE BOND PADS FOR HUMAN IMPLANT APPLICATIONS 50 2006
 
BROADCOM CORPORATION (1)
* 2007/0290,376 Integrated circuit (IC) package stacking and IC packages formed by same 181 2006
 
Beyond Blades Ltd. (1)
* 2008/0253,085 3-Dimensional Multi-Layered Modular Computer Architecture 48 2006
 
INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE (1)
* 2006/0091,542 Flip chip package including a heat spreader having an edge with a recessed edge portion and method of making the same 20 2004
* Cited By Examiner

Patent Citation Ranking

Forward Cite Landscape

Patent Info (Count) # Cites Year
 
QUALCOMM INCORPORATED (4)
* 8,742,603 Process for improving package warpage and connection reliability through use of a backside mold configuration (BSMC) 0 2010
* 2011/0285,026 Process For Improving Package Warpage and Connection Reliability Through Use Of A Backside Mold Configuration (BSMC) 2 2010
8,461,676 Soldering relief method and semiconductor device employing same 0 2011
8,841,168 Soldering relief method and semiconductor device employing same 0 2013
 
STATS CHIPPAC PTE. LTE. (5)
7,888,184 Integrated circuit packaging system with embedded circuitry and post, and method of manufacture thereof 7 2009
8,957,530 Integrated circuit packaging system with embedded circuitry and post 0 2011
* 2011/0127,678 INTEGRATED CIRCUIT PACKAGING SYSTEM WITH EMBEDDED CIRCUITRY AND POST 1 2011
* 8,994,184 Semiconductor device and method of forming interposer and opposing build-up interconnect structure with connecting conductive TMV for electrical interconnect of FO-WLCSP 0 2013
* 2013/0241,080 Semiconductor Device and Method of Forming Interposer and Opposing Build-Up Interconnect Structure with Connecting Conductive TMV for Electrical Interconnect of FO-WLCSP 2 2013
 
MITSUBISHI ELECTRIC CORPORATION (1)
9,171,772 Semiconductor device 0 2013
 
RENESAS ELECTRONICS CORPORATION (5)
* 8,159,058 Semiconductor device having wiring substrate stacked on another wiring substrate 7 2008
* 2009/0065,773 SEMICONDUCTOR DEVICE 3 2008
8,698,299 Semiconductor device with wiring substrate including lower conductive pads and testing conductive pads 1 2012
8,766,425 Semiconductor device 1 2013
9,330,942 Semiconductor device with wiring substrate including conductive pads and testing conductive pads 0 2014
 
SAMSUNG ELECTRONICS CO., LTD. (2)
* 8,824,163 RF layered module using three dimensional vertical wiring and disposing method thereof 0 2011
* 2012/0063,106 RF LAYERED MODULE USING THREE DIMENSIONAL VERTICAL WIRING AND DISPOSING METHOD THEREOF 0 2011
* Cited By Examiner