Memory array error correction apparatus, systems, and methods

Number of patents in Portfolio can not be more than 2000

United States of America Patent

PATENT NO 7945840
APP PUB NO 20080195894A1
SERIAL NO

11705190

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ATTORNEY / AGENT: (SPONSORED)

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Abstract

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Various embodiments include apparatus, methods, and systems that operate to extend the processes of reading, modifying, and writing data stored in or being provided to a memory array without interrupting a continual stream of data to be written into the memory array. Embodiments may include an apparatus comprising a memory array, and an error code module coupled to the memory array with a data buffer having a plurality of data burst registers operable to receive a plurality of data bursts to be written to the memory array on a corresponding plurality of consecutive clock cycles. The error code module is operable to perform a read/modify/write process on each of the plurality of data bursts within a time period no longer than a period of two consecutive cycles of the plurality of consecutive clock cycles.

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Patent Owner(s)

Patent OwnerAddress
U S BANK NATIONAL ASSOCIATION AS COLLATERAL AGENT100 WALL STREET SUITE 1600 NEW YORK NY 10005

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Dauenbaugh, Todd A Richardson, US 8 162
Schreck, John F Lucas, US 79 1367

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