Isolated quasi-vertical DMOS transistor
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United States of America Patent
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app pub date -
Feb 27, 2008
filing date -
Aug 14, 2002
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Abandoned
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Abstract
Various integrated circuit devices, in particular a quasi-vertical DMOS transistor, are formed inside an isolation structure which includes a floor isolation region and a trench extending from the surface of the substrate to the floor isolation region. The trench may be filled with a dielectric material or may have a conductive material in a central portion with a dielectric layer lining the walls of the trench. Various techniques for terminating the isolation structure by extending the floor isolation region beyond the trench, using a guard ring, and a forming a drift region are described.
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