Guard wafer for semiconductor structure fabrication
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United States of America Patent
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Feb 10, 2009
Grant Date -
Sep 4, 2008
app pub date -
Apr 11, 2008
filing date -
Apr 4, 2005
priority date (Note) -
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status (Latency Note)
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Abstract
An apparatus which allows tightly coupling of the device wafer to the electrostatic chuck of the process chamber after the process chamber is conditioned. The apparatus includes (a) a process chamber; (b) a chuck in the process chamber; (c) a guard wafer placed on and in direct physical contact with the chuck; and (d) a particle restraining layer on essentially all surfaces that are exposed to the ambient inside the process chamber. The particle restraining layer has a thickness in a first direction of at least 500 nm. The first direction is essentially perpendicular to an interfacing surface between the particle restraining layer and the chuck. The guard wafer comprises a material selected from the group consisting of a metal and a semiconductor oxide.
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