Digital delay architecture
Number of patents in Portfolio can not be more than 2000
United States of America Patent
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N/A
Issued Date -
Sep 18, 2008
app pub date -
Mar 13, 2007
filing date -
Mar 13, 2007
priority date (Note) -
Abandoned
status (Latency Note)
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Abstract
A digital delay architecture and a digital delay method are provided. The digital delay architecture includes at least one shifter, at least one adder connected to the at least one shifter and a plurality of registers storing at least an output of the at least one adder and an original sampled signal. The plurality of registers are selectable to define a fractional delay value.
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