Intelligent solid-state non-volatile memory device (NVMD) system with multi-level caching of multiple channels
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United States of America Patent
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May 1, 2012
Grant Date -
Sep 25, 2008
app pub date -
May 5, 2008
filing date -
Jan 6, 2000
priority date (Note) -
Expired
status (Latency Note)
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Abstract
A flash memory system stores blocks of data in Non-Volatile Memory Devices (NVMD) that are addressed by a logical block address (LBA). The LBA is remapped for wear-leveling and bad-block relocation by the NVMD. The NVMD are interleaved in channels that are accessed by a NVMD controller. The NVMD controller has a controller cache that caches blocks stored in NVMD in that channel, while the NVMD also contain high-speed cache. The multiple levels of caching reduce access latency. Power is managed in multiple levels by a power controller in the NVMD controller that sets power policies for power managers inside the NVMD. Multiple NVMD controllers in the flash system may each controller many channels of NVMD. The flash system with NVMD may include a fingerprint reader for security.
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