Transition areas for dense memory arrays
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United States of America Patent
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app pub date -
Apr 29, 2008
filing date -
Nov 25, 2005
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Abstract
A non-volatile memory chip has word lines spaced a sub-F (sub-minimum feature size F) width apart with extensions of the word lines in at least two transition areas. Neighboring extensions are spaced at least F apart. The present invention also includes a method for word-line patterning of a non-volatile memory chip which includes generating sub-F word lines with extensions in transition areas for connecting to peripheral transistors from mask generated elements with widths of at least F.
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