METHOD FOR ACCELERATING THE GENERATION OF AN OPTIMIZED GATE-LEVEL REPRESENTATION FROM A RTL REPRESENTATION
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United States of America Patent
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Issued Date -
Oct 2, 2008
app pub date -
Mar 29, 2007
filing date -
Mar 29, 2007
priority date (Note) -
Abandoned
status (Latency Note)
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Abstract
A method for accelerating the generation of an optimized netlist from a RTL representation is provided. The method optimizes a given RTL description of an integrated circuit (IC) design by: generating a static single assignment (SSA) graph; creating value range propagation for each variable in the SSA graph; and, applying one or more of a set of optimization algorithms on the SSA graph. The optimization algorithms include, but are not limited to, dead-code elimination, bitwidth analysis, redundancy elimination, iteration loop optimization, algebraic simplification and so on. These algorithms operate on a word-level description to enable fast optimization. Furthermore, the optimized RTL accelerates the overall flow of an IC design.
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