METHOD AND APPARATUS FOR WRITING BINARY DATA WITH LOW POWER CONSUMPTION
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United States of America Patent
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Issued Date -
Oct 9, 2008
app pub date -
Apr 3, 2008
filing date -
Apr 4, 2007
priority date (Note) -
Abandoned
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Abstract
Systems and methodologies are provided herein for representing information in a data processing system with low power consumption. As described herein, parity relationships between multiple nodes of to-be-written binary information and original information can be leveraged as described herein to reduce the amount of toggling required to write information in a memory, thereby reducing power consumption. Various algorithms for leveraging parity relationships are described herein, including a Champagne Pyramid Parity Check (CPPC) algorithm and a Tree-Based Parity Check (TBPC) algorithm.
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