IMPLEMENTATION OF PATCHES BY A PROCESSING UNIT
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United States of America Patent
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Issued Date -
Oct 23, 2008
app pub date -
Apr 18, 2008
filing date -
Apr 19, 2007
priority date (Note) -
Abandoned
status (Latency Note)
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Abstract
A method and a circuit of execution, by a processing unit, of at least one patch of at least one first program stored in a first non-reprogrammable non-volatile memory, the patch being stored in a second memory, and wherein: each current address of an instruction of the first program provided by the processing unit is compared with values preloaded in at least one volatile storage element; in case of an identity between the current address and a preloaded value, an interrupt is triggered, this interrupt triggering a search, from a correspondence table, for an address of a patch in the second memory; and the patch is executed.
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