INTEGRATED CIRCUIT PACKAGE WITH SOLDERED LID FOR IMPROVED THERMAL PERFORMANCE

United States of America Patent

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Issued Date
Nov 27, 2008
app pub date
May 25, 2007
filing date
May 25, 2007

priority date (Note)
Abandoned

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Abstract

An integrated circuit die includes a circuit surface and a back surface opposite the circuit surface. An underbump metallurgy is formed on a back surface. A layer of solder is formed on the underbump metallurgy.

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Patent Owner(s)

Patent Owner	Address
LSI LOGIC CORPORATION	1621 BARBER LANE MS AD-106 MILPITAS CA 95035

International Classification(s)

H01L:SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICE....

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[Patents Count]

Inventor(s)

Inventor Name	Address	# of filed Patents	Total Citations
Kutlu, Zafer	Menlo Park, CA	14	30

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INTEGRATED CIRCUIT PACKAGE WITH SOLDERED LID FOR IMPROVED THERMAL PERFORMANCE

Number of patents in Portfolio can not be more than 2000

United States of America Patent

11753591

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APP PUB NO	20080290502A1
SERIAL NO	11753591
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11753591

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Abstract

First Claim

Family

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