Chip Scale Package and Method of Assembling the Same
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United States of America Patent
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N/A
Issued Date -
Nov 27, 2008
app pub date -
Dec 2, 2004
filing date -
Dec 2, 2003
priority date (Note) -
Abandoned
status (Latency Note)
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Abstract
A method of producing a chip scale package is disclosed. The method includes dicing a wafer into a plurality of chip arrays, each array including two or more integrated circuit chips. The method further includes mounting each array on a substrate and dicing each array, attached to the substrate, into individual chip scale packages, each individual chip scale package including only one integrated circuit chip.
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