Method of destructive testing the dielectric layer of a semiconductor wafer or sample

Number of patents in Portfolio can not be more than 2000

United States of America Patent

APP PUB NO 20080290889A1
SERIAL NO

11805788

Stats

ATTORNEY / AGENT: (SPONSORED)

Importance

Loading Importance Indicators... loading....

Abstract

See full text

In a method of testing a semiconductor wafer or sample having a dielectric layer overlaying a substrate of semiconducting material, a contact is caused to touch a top surface of the dielectric layer. At least a portion of the contact touching the dielectric layer is formed of iridium. A controlled electrical stimulus that causes the dielectric layer to breakdown and an electrically conductive path to form through the dielectric layer is applied to the contact touching the top surface of the dielectric layer. Either a value of the controlled electrical stimulus where breakdown of the dielectric layer occurs or a time for the breakdown of the dielectric layer to occur in response to the application of the controlled electrical stimulus is determined. From the thus determined value or time, a determination can be made whether the dielectric layer is within acceptable tolerance.

Loading the Abstract Image... loading....

First Claim

See full text

Family

Loading Family data... loading....

Patent Owner(s)

Patent OwnerAddress
SOLID STATE MEASUREMENTS INC110 TECHNOLOGY DRIVE PITTSBURGH PA 15275

International Classification(s)

  • [Classification Symbol]
  • [Patents Count]

Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Hillard, Robert J Avalon, PA 15 186

Cited Art Landscape

Load Citation

Patent Citation Ranking

Forward Cite Landscape

Load Citation