Stage yield prediction

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United States of America Patent

PATENT NO 7962864
APP PUB NO 20080295047A1
SERIAL NO

12154458

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Abstract

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In one embodiment, a method for predicting yield during the design stage includes receiving defectivity data identifying defects associated with previous wafer designs, and dividing the defects into systematic defects and random defects. For each design layout of a new wafer design, yield is predicted separately for the systematic defects and the random defects. A combined yield is then calculated based on the yield predicted for the systematic defects and the yield predicted for the random defects.

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Patent Owner(s)

Patent OwnerAddress
APPLIED MATERIALS INC3050 BOWERS AVENUE SANTA CLARA CA 95054

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Jawaharlal, Sundar Glen Allen, US 4 113
Nehmadi, Youval Modiin, IL 31 856
Schwarm, Alexander T Austin, US 35 1146
Shimshi, Rinat San Jose, US 10 305
Svidenko, Vicky San Jose, US 16 493

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