Buffer minimization in interface controller
Number of patents in Portfolio can not be more than 2000
United States of America Patent
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Oct 9, 2012
Grant Date -
Dec 4, 2008
app pub date -
Jun 1, 2007
filing date -
Jun 1, 2007
priority date (Note) -
In Force
status (Latency Note)
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Abstract
In one embodiment, an apparatus comprises serializer/deserializer (SERDES) circuits. Each SERDES circuit is configured to transmit data on a respective lane to which the SERDES circuit is are coupled during use. The apparatus further comprises a transmit pipe coupled to the SERDES circuits. The transmit pipe comprises stages, and each stage is configured to process a maximum bandwidth unit (a maximum width of a port that is configurable on the lanes and smaller than a largest packet transmitted on the ports). In another embodiment, the apparatus comprises a transmit command queue; a transmit scheduler coupled to the transmit command queue; and a storage device coupled to the transmit scheduler that stores a scheduling calendar. The transmit scheduler is configured to schedule maximum bandwidth units for transmission on ports configured over the lanes on which packets are transmitted. The maximum bandwidth unit is smaller than a packet and is a maximum width of a port that is configurable on the lanes. The transmit scheduler is configured to schedule the maximum bandwidth units according to the scheduling calendar.
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