CMOS Compatible Single-Poly Non-Volatile Memory
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United States of America Patent
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Issued Date -
Dec 18, 2008
app pub date -
Jun 18, 2007
filing date -
Jun 18, 2007
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Abandoned
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Abstract
The present invention teaches a single-poly non-volatile memory cell which is compatible with the CMOS process, uses lower voltages for operating, and is more reliable in program, read, or erase operation. The single-poly non-volatile memory cell in accordance with the present invention comprises a program transistor with a program terminal; a sensing transistor with a sensing terminal; and an erase transistor with an erase terminal, wherein the sensing transistor shares a floating gate with the program transistor and the erase transistor. By employing the present invention, significant cost advantages in feature-rich semiconductor products, such as System-on-Chip (SoC) design, compared to conventional dual-poly floating gate embedded Flash memory are provided.
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