Vertical NPN Transistor Fabricated in a CMOS Process With Improved Electrical Characteristics
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United States of America Patent
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Issued Date -
Jan 29, 2009
app pub date -
Jul 27, 2007
filing date -
Jul 27, 2007
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Abstract
A vertical NPN bipolar transistor includes a P-type semiconductor structure, an N-well as the collector, a P-Base region in the N-well and an N-type region as the emitter. The transistor further includes P-type region formed in the P-Base region and underneath the field oxide layer where the P-type region has a doping concentration higher than the P-base region. The P-type region functions to inhibit the lateral parasitic bipolar action so that the transistor action is confined to the intrinsic base region vertically underneath the emitter. In one embodiment, the P-type region is a boron field doping region. The boron field doping region can be the same field doping region used to form channel stops for NMOS transistors in a CMOS fabrication process.
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