SYSTEMS AND METHODS FOR ON-CHIP POWER MANAGEMENT
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United States of America Patent
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app pub date -
Sep 3, 2008
filing date -
Mar 21, 2007
priority date (Note) -
Abandoned
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Abstract
A power measurement system is disclosed for use on an integrated circuit for measuring the power used by the integrated circuit. The power measurement system includes a low-dropout voltage regulator and a signal input unit. The low-dropout voltage regulator includes a power transistor that couples a supply voltage to a circuit to be powered by the supply voltage, and the low-dropout voltage regulator provides an internal adjustment signal (V.sub.sen) for adjusting the internal resistance of the power transistor. The signal input unit receives the internal adjustment signal (V.sub.sen) and provides a power measurement signal responsive to the internal adjustment signal (V.sub.sen).
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