Processor, data transfer unit, multicore processor system
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United States of America Patent
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Feb 1, 2011
Grant Date -
Mar 5, 2009
app pub date -
Jul 14, 2008
filing date -
Aug 29, 2007
priority date (Note) -
Expired
status (Latency Note)
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Abstract
A processor includes a CPU capable of performing predetermined arithmetic processing, a memory accessible by the CPU, and a data transfer unit capable of controlling data transfer with the memory by substituting for the CPU. The data transfer unit is provided with a command chain unit for continuously performing data transfer by execution of a preset command chain, and a retry controller for executing a retry processing in case a transfer error occurs during data transfer by the command chain unit. Then, the data transfer unit reports a command relating to the transfer error to the CPU after completion of the execution of the command chain, thereby lessening the number of interruptions for error processing, and attaining enhancement in performance of a system.
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