Non-volatile memory and method for biasing adjacent word line for verify during programming

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United States of America Patent

PATENT NO 7652929
APP PUB NO 20090073771A1
SERIAL NO

11856639

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Abstract

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Various programming techniques for nonvolatile memory involve programming a memory cell relative to a target threshold level. The process includes initially programming relative to a first verify level short of the target threshold level by a predetermined offset. Later, the programming is completed relative to the target verify level. For verifying with the first verify level, a virtual first verify level is effectively used where the target threshold level is used on a selected word line and a bias voltage is used on an adjacent unselected word line. Thus, the verify level in a first programming pass or programming phase is preferably virtually offset by biasing one or more adjacent word line instead of actually offsetting the standard verify level in order to avoid verifying at low levels.

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Patent Owner(s)

  • SANDISK TECHNOLOGIES LLC

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Li, Yan Milpitas, US 1320 19576

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