Importance

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Abstract

A reconfigurable arithmetic circuit including a matrix having a plurality of partial product mask cells arranged in rows and columns, where rows and columns have incrementing arithmetic weights assigned, each partial product mask cell including a gate implementing a logical AND function of its inputs to provide an output, and a programmable memory cell connected to furnish input to the gate, a plurality of horizontally oriented conductors each connected to furnish input to the gates of the partial product mask cells of a row, and a plurality of diagonally oriented conductors each connected to furnish input to the gates of the partial product mask cells along the diagonal of increasing arithmetic weight of rows and columns, and a compression circuit receiving inputs from the gates of the partial product mask cells of the matrix, and furnishing outputs providing conventional arithmetic compression of its inputs in carry-saved format.

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First Claim