Reconfigurable arithmetic unit
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United States of America Patent
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Issued Date -
Mar 19, 2009
app pub date -
Sep 14, 2007
filing date -
Sep 14, 2007
priority date (Note) -
Abandoned
status (Latency Note)
Importance
Abstract
A reconfigurable arithmetic circuit including a plurality of logical AND gates arranged in logical columns and rows, a plurality of conductors each connected to furnish input to the AND gates of a row, an array of memory cells each connected to furnish input to one of the AND gates, and a plurality of reconfigurable counting circuits, each counting circuit connected to receive the output of each of the AND gates in a column, each counting circuit being configurable to provide a count of parity of the outputs furnished by the AND gates of the column.
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