TRENCH MOSFET AND METHOD OF MANUFACTURE UTILIZING THREE MASKS

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United States of America Patent

SERIAL NO

11866353

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Abstract

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In accordance with the invention a vertical power trench MOSFET semiconductor device comprises P+ body and N+ source diffusions shorted together to prevent second breakdown caused by a parasitic bipolar transistor. The device is manufactured in accordance with a process comprising the steps of: providing a heavily doped N+ silicon substrate; utilizing a first, trench, mask to define a plurality of openings comprising a trench gate and a termination; creating P+ body and N+ source area formations by ion implantation without any masks; utilizing a second, contact, mask to define a gate bus area; and utilizing a third metal mask to separate source metal and gate bus metal and remove metal from a portion of the termination, whereby only three masks are utilized to form the semiconductor device.

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Patent Owner(s)

Patent OwnerAddress
INPOWER SEMICONDUCTOR CO LTD9 DAI SHUN STREET TAI PO IND ESTATE TAI PO N T

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Chen, Tai Chiang Tianjin, CN 4 43
Lv, Long Tianjin, CN 3 41
Su, Shih Tzung Shulin City, TW 3 41
Sun, Poi Torrance, US 3 41
Tu, Kao Way Jhonghe City, TW 4 41
Wang, Xin Tianjin , CN 596 5154
Zeng, Jun Torrance, US 177 1418

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