TRENCH MOSFET AND METHOD OF MANUFACTURE UTILIZING THREE MASKS

Number of patents in Portfolio can not be more than 2000

United States of America Patent

APP PUB NO 20090085099A1
SERIAL NO

11866353

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ATTORNEY / AGENT: (SPONSORED)

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Abstract

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In accordance with the invention a vertical power trench MOSFET semiconductor device comprises P+ body and N+ source diffusions shorted together to prevent second breakdown caused by a parasitic bipolar transistor. The device is manufactured in accordance with a process comprising the steps of: providing a heavily doped N+ silicon substrate; utilizing a first, trench, mask to define a plurality of openings comprising a trench gate and a termination; creating P+ body and N+ source area formations by ion implantation without any masks; utilizing a second, contact, mask to define a gate bus area; and utilizing a third metal mask to separate source metal and gate bus metal and remove metal from a portion of the termination, whereby only three masks are utilized to form the semiconductor device.

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Patent Owner(s)

Patent OwnerAddressTotal Patents
Inpower Semiconductor Co., Ltd.TAI PO NT, HK1

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Chen, Tai Chiang Tianjin, CN 4 37
Lv, Long Tianjin, CN 3 35
Su, Shih Tzung Shulin City, TW 3 35
Sun, Poi Torrance, US 3 35
Tu, Kao Way Jhonghe City, TW 4 35
Wang, Xin Tianjin , CN 459 4233
Zeng, Jun Torrance, US 144 1267

Cited Art Landscape

Patent Info (Count) # Cites Year
 
Inpower Semiconductor Co., Ltd. (3)
* 2009/0085,074 TRENCH MOSFET AND METHOD OF MANUFACTURE UTILIZING FOUR MASKS 11 2007
* 2009/0085,105 TRENCH MOSFET AND METHOD OF MANUFACTURE UTILIZING TWO MASKS 18 2007
* 7687352 Trench MOSFET and method of manufacture utilizing four masks 2 2007
 
M-MOS SEMICONDUCTOR SDN. BHD. (1)
* 2006/0273,382 High density trench MOSFET with low gate resistance and reduced source contact space 27 2005
 
TRANSPACIFIC IP II LTD. (1)
* 2005/0266,623 Trench power MOSFET in silicon carbide and method of making the same 0 2004
 
ALPHA & OMEGA SEMICONDUCTOR, LTD. (1)
* 2002/0030,224 MOSFET POWER DEVICE MANUFACTURED WITH REDUCED NUMBER OF MASKS BY FABRICATION SIMPLIFIED PROCESSES 10 1997
 
Semiconductor Energy Laboratory Co., Ltd. (1)
* 5604137 Method for forming a multilayer integrated circuit 104 1995
 
ALPHA AND OMEGA SEMICONDUCTOR INCORPORATED (1)
* 2006/0170,036 Method of fabricating semiconductor device containing dielectrically isolated PN junction for enhanced breakdown characteristics 12 2006
 
HARRIS CORPORATION (1)
* 2002/0195,653 Semiconductor structures with trench contacts 1 2002
* Cited By Examiner

Patent Citation Ranking

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Patent Info (Count) # Cites Year
 
VISHAY-SILICONIX (4)
9484451 MOSFET active area and edge termination area charge balance 1 2008
9431249 Edge termination for super junction MOSFET devices 1 2011
9614043 MOSFET termination trench 1 2012
9508596 Processes used in fabricating a metal-insulator-semiconductor field effect transistor 0 2014
* Cited By Examiner