TRENCH MOSFET AND METHOD OF MANUFACTURE UTILIZING THREE MASKS
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United States of America Patent
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app pub date -
Oct 2, 2007
filing date -
Oct 2, 2007
priority date (Note) -
Abandoned
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Abstract
In accordance with the invention a vertical power trench MOSFET semiconductor device comprises P+ body and N+ source diffusions shorted together to prevent second breakdown caused by a parasitic bipolar transistor. The device is manufactured in accordance with a process comprising the steps of: providing a heavily doped N+ silicon substrate; utilizing a first, trench, mask to define a plurality of openings comprising a trench gate and a termination; creating P+ body and N+ source area formations by ion implantation without any masks; utilizing a second, contact, mask to define a gate bus area; and utilizing a third metal mask to separate source metal and gate bus metal and remove metal from a portion of the termination, whereby only three masks are utilized to form the semiconductor device.
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