Trench MOSFET and method of manufacture utilizing two masks

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United States of America Patent

PATENT NO 7799642





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A method for manufacturing a trench MOSFET semiconductor device comprises: providing a heavily doped N+ silicon substrate; forming an N type epitaxial layer; forming a thick SiO2 layer; creating P body and source area formations by ion implantation without any masks; utilizing a first mask to define openings for a trench gate and a termination; thermally growing a gate oxide layer followed by formation of a thick poly-Silicon refill layer without a mask to define a gate bus area; forming sidewall spacers; forming P+ areas; removing the sidewall spacers; depositing tungsten to fill contacts and vias; depositing a first thin barrier metal layer; depositing a first thick metal layer; utilizing a second metal mask to open a gate bus area; forming second sidewall spacers; depositing a second thin barrier metal layer; depositing a second thick metal layer; and planarizing at least the second thick metal layer and the second thin metal layer to isolate the source metal portions from gate metal portions, whereby the trench MOSFET semiconductor device is manufactured utilizing only first and second masks.

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Patent Owner(s)

Patent OwnerAddressTotal Patents
Inpower Semiconductor Co., Ltd.TAI PO NT, HK1

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Inventor Name Address # of filed Patents Total Citations
Chen, Tai Chiang TianJin, CN 4 43
Lv, Long TianJin, CN 3 41
Su, Shih Tzung Shulin, TW 3 41
Sun, Poi Torrance, US 3 41
Tu, Kao Way Jhonghe, TW 4 41
Wang, Xin TianJin, CN 579 4998
Zeng, Jun Torrance, US 173 1403

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