Processor architecture for executing transfers between wide operand memories
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United States of America Patent
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Issued Date -
Apr 2, 2009
app pub date -
Oct 31, 2007
filing date -
Aug 24, 1998
priority date (Note) -
Abandoned
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Abstract
A programmable processor and method for improving the performance of processors by expanding at least two source operands, or a source and a result operand, to a width greater than the width of either the general purpose register or the data path width. The present invention provides operands which are substantially larger than the data path width of the processor by using the contents of a general purpose register to specify a memory address at which a plurality of data path widths of data can be read or written, as well as the size and shape of the operand. In addition, several instructions and apparatus for implementing these instructions are described which obtain performance advantages if the operands are not limited to the width and accessible number of general purpose registers.
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