On-chip inductors with through-silicon-via fence for Q improvement
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United States of America Patent
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Jul 23, 2013
Grant Date -
Apr 9, 2009
app pub date -
Oct 5, 2007
filing date -
Oct 5, 2007
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Abstract
A semiconductor structure for providing isolations for on-chip inductors comprises a semiconductor substrate, one or more on-chip inductors formed above the first semiconductor substrate, a plurality of through-silicon-vias formed through the first semiconductor substrate in a vicinity of the one or more on-chip inductors, and one or more conductors coupling at least one of the plurality of through-silicon-vias to a ground, wherein the plurality of through-silicon-vias provide isolations for the one or more on-chip inductors.
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