Method for making a self-converged void and bottom electrode for memory cell
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United States of America Patent
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Dec 29, 2009
Grant Date -
Apr 23, 2009
app pub date -
Dec 15, 2008
filing date -
Dec 6, 2006
priority date (Note) -
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Abstract
A base layer, comprising an electrically conductive element, is formed. An upper layer, including a third, lower planarization stop layer, a second layer and a first, upper layer is formed on the base layer. A keyhole opening is formed through the upper layer to expose a surface of an electrically conductive element in the base layer. The first layer has an overhanging portion extending into the opening so that the opening in the first layer is shorter than in the second layer. A dielectric material is deposited into the keyhole opening to create a self-converged void within the deposited dielectric material. In some examples the keyhole forming step comprises increasing the volume of the first layer while in other examples the keyhole forming step comprises etching back the second layer.
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