Hierarchical bus structure and memory access protocol for multiprocessor systems
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United States of America Patent
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May 29, 2012
Grant Date -
Apr 23, 2009
app pub date -
Dec 22, 2008
filing date -
Feb 19, 2002
priority date (Note) -
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Abstract
A hierarchical bus structure is disclosed in which clusters of processors are arranged and interconnected within a hierarchy to facilitate processor communications via shared memories. The bus structure is well suited for voice processing applications in which clusters of embedded processors process voice streams in parallel, although the architecture is not so limited. Also disclosed is a memory access protocol in which the address and data portions of shared-memory access operations are performed as separate bus transactions that are separated in time, such that multiple concurrent memory access operations from different processors may be interleaved over a shared bus.
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