Buffer circuit with reduced power consumption
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United States of America Patent
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Dec 1, 2009
Grant Date -
May 7, 2009
app pub date -
Jun 8, 2006
filing date -
Jun 10, 2005
priority date (Note) -
In Force
status (Latency Note)
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Abstract
A buffer circuit is provided, having an odd number of stages of inverting amplifiers, wherein the stages are capacitive coupled. A negative feedback path feeds back from an output terminal of the final stage of the inverting amplifiers to an input terminal of the initial stage. A reference current source is also provided. A first switch is provided between the adjacent stages of the inverting amplifiers and switched, depending upon a mode of operation. A second switch is provided for selectively driving at least a transistor(s) in the final stage to cause a current mirror circuit with the reference current source depending upon a mode of operation.
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