Method and Apparatus of Automatically Selecting Error Correction Algorithms by a NAND Flash Controller
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United States of America Patent
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Issued Date -
May 14, 2009
app pub date -
Nov 13, 2007
filing date -
Nov 13, 2007
priority date (Note) -
Abandoned
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Abstract
A method and apparatus of automatically selecting an optimal ECC algorithm by NAND Flash controller to detect and correct errors to read or write data from or to a flash memory device is described. In one embodiment, the method includes selecting the optimal algorithm by identifying the characteristics of the target flash memory device such as but not limited to redundant data size. The method also includes determining the optimal algorithm based on the application stored in the target flash memory device.
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